Implementation of 12 bit R-2R DAC using cadence(90nm)

https://doi.org/10.53730/ijhs.v6nS2.7771

Authors

  • K. Saravanan Assistant Professor, Electronics and Communication Engineering, Veltech Multitech Dr.Ragarajan & Dr.Sakunthala Engineering College, Avadi-600062, Tamilnadu, India
  • S. Tamilmani UG Student, Department of ECE, Veltech Multitech Dr.Ragarajan & Dr.Sakunthala Engineering College, Avadi-600062, Tamilnadu, India
  • S. Deepak Surendar UG Student, Department of ECE, Veltech Multitech Dr.Ragarajan & Dr.Sakunthala Engineering College, Avadi-600062, Tamilnadu, India
  • B. Dinesh Kumar UG Student, Department of ECE, Veltech Multitech Dr.Ragarajan & Dr.Sakunthala Engineering College, Avadi-600062, Tamilnadu, India

Keywords:

DAC, cadence, R-2R

Abstract

An R-2R DAC utilizes less special esteem which is in contrast with to the binary weighed- input DAC. Continuous sampling and measuring of an analog signal occurs over time. This project depends on R-2R Ladder for investing Low power utilization, no dynamic chip and Low DNL. The DAC is executed in a virtuoso device on 90 Nanometer CMOS Technology. The two stages in our projects seems to be Operational Amplifier and R-2R Ladder Digital to analog converters enable transmission of analog signals over digital signal processing chips [1].Two stages are involved in the OP-Amp, the first one being a differential amplifier. We use this Differential Amplifier to obtain high gain and second stage namely Common Source Amplifier. It increases Gain that leaded from the first stage and increases it Output swing. In our project,R-2R DAC is implemented using CADENCE 90nm tool.

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References

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Published

23-05-2022

How to Cite

Saravanan, K., Tamilmani, S., Surendar, S. D., & Kumar, B. D. (2022). Implementation of 12 bit R-2R DAC using cadence(90nm). International Journal of Health Sciences, 6(S2), 11114–11123. https://doi.org/10.53730/ijhs.v6nS2.7771

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Section

Peer Review Articles